1. Field of the Invention
The present invention relates in general to a differential subtracter circuit and an analog/digital converter, and in particular, to improvement of operation accuracy of a differential subtracter circuit and an analog/digital converter. The present invention is particularly applicable to an analog/digital converter of a two-step parallel type.
2. Description of the Background Art
Converters for converting analog signals into digital signals (referred to as "A/D converters" hereinafter) have been widely used for applying digital signal processing to the analog signals. High-speed processing of digital signals with high accuracy is required, for example, in a field of video signal processing, and therefore the high-speed conversion with high accuracy is required in the A/D converters.
A/D converters employing to various converting methods have been known. As is generally known, among them a two-step parallel A/D converter is suitable to signal processing for images requiring high definition. Such signal processing is required, for example, in high definition televisions, video tape recorders (VTRs) for business use and digital video cameras. Examples of the two-step parallel A/D converter are disclosed in:
(a) a paper entitled "A 10-b 75-MSPS Subranging A/D Converter with Integrated Sample and Hold" (IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, Dec. 1990), and
(b) a paper entitled "A 10-bit 20-MHz Two-Step Parallel A/D Converter with Internal S/H" (IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, Feb. 1989).
FIG. 5 is a block diagram of a two-step parallel A/D converter in the prior art. The foregoing references have disclosed circuits similar to those of the A/D converter shown in FIG. 5. Referring to FIG. 5, an A/D converter 100 includes a sample hold circuit (S/H) 2, an A/D converter (ADC) 6 for higher bits, a D/A converter (DAC) 7 for higher bits, a subtracter 3, an A/D converter (ADC) 8 for lower bits, encoders 10a and 10b for higher and lower bits, and an output latch circuit 9.
The sample hold circuit 2 receives a differential input signal .DELTA.Van to be converted into a digital signal, and supplies a sample-held differential signal .DELTA.Vsh. The differential signal .DELTA.Vsh is defined by two held voltages V1 and V2. These voltages V1 and V2 are supplied to the differential subtracter 3 and the A/D converter 6. An externally applied differential reference voltage .DELTA.Vref is supplied to a coarse reference voltage generating circuit 5a and the D/A converter 7. The A/D converter 6 compares the differential voltage signal .DELTA.Vsh with a coarse reference voltage Vcr to convert the differential voltage signal .DELTA.Vsh into complementary digital signals (thermometer codes) S1-S8 and B1-B8, which are applied to the D/A converter 7 and encoder 10a.
The D/A converter 7 is responsive to the applied complementary digital signals S1-S8 and B1-B8 to supply corresponding differential current signals Is1 and Is2, which correspond to converted higher bit signal.
The differential subtracter 3 subtracts the differential current signals Is1 and Is2 from differential current signal (not shown) corresponding to the differential voltage signal .DELTA.Vsh. Differential subtraction signals Vo1 and Vo2 showing a result of subtraction are applied to the A/D converter 8.
A fine reference voltage generating circuit 5b applies a plurality of fine reference voltages Vfr to the A/D converter 8. The A/D converter 8 compares the differential subtraction signals Vo1 and Vo2 with the applied fine reference voltages. Lower bit signals (thermometer codes) showing results of comparison are applied to the lower bit encoder 10b.
The encoders 10a and 10b convert the applied thermometer codes of higher bits and the applied thermometer codes of lower bits, e.g., into straight binary codes, and data signals thus converted are applied to the output latch circuit 9. The output latch circuit 9 supplies the received data signals as output data signals D1, D2, . . . , Dm.
FIG. 6 is a circuit diagram showing the coarse reference voltage generating circuit 5a and the higher bit A/D converter 6. Referring to FIG. 6, the coarse reference voltage generating circuit 5a includes a ladder resistor circuit formed of resistors 501-509 connected in series. The externally received differential reference voltage .DELTA.Vref is applied across opposite ends of the ladder resistor circuit. The coarse reference voltage generating circuit 5a supplies coarse reference voltages Vcr1-Vcr8 through common connection nodes, each of which is common to adjacent two resistors, respectively.
The A/D converter 6 includes comparators 61-68 each receiving the differential voltage signal .DELTA.Vsh. The comparators 61-68 receive the corresponding coarse reference voltages Vcr1-Vcr8 to compare the differential voltage signal .DELTA.Vsh with the corresponding coarse reference voltages Vcr1-Vcr8, respectively. The A/D converter 6 supplies the complementary digital signals (thermometer codes) S1-S8 and B1-B8 indicative of the result of comparison. The signals S1-S8 are complementary with the corresponding signals B1-B8, respectively. The complementary signals S1-S8 and B1-B8 are applied to the A/D converter 7 in FIG. 5 and are also applied to the higher bit encoder 10a.
FIG. 7 is a circuit diagram of the fine reference voltage generating circuit 5b shown in FIG. 5. Referring to FIG. 7, the fine reference voltage generating circuit 5b includes a differential amplifier 510, a constant current supply circuit 520, an input resistor 511, and a ladder resistor circuit 517. The constant current supply circuit 520 includes npn transistors 512 and 513, emitter resistors 514 and 515, and a constant current supply 516. By the function of constant current supply circuit 520, a current If flows through the input resistor 511. A voltage difference between opposite ends of the input resistor 511 is applied to the differential amplifier 510 through terminals + and -.
The differential output voltage of the differential amplifier 510 is applied across the opposite ends of the ladder resistor circuit 517, which in turn supplies fine reference voltages Vfr1-Vfr8. The fine reference voltages Vfr1-Vfr8 subdivides one voltage range among those of the coarse reference voltages Vcr1-Vcr8 shown in FIG. 6. The fine reference voltages Vfr1-Vfr8 are applied to the A/D converter 8.
FIG. 8 is a circuit diagram of the differential subtracter circuit 3 and D/A converter 7 in the prior art shown in FIG. 5. Referring to FIG. 8, the D/A converter 7 includes the subtraction current generating circuits 71, 72, . . . , 7n. Each of the subtraction current generating circuits 71-7n draws in the current through one of current lines CL1 and CL2 in response to corresponding one pair of the complementary digital signals B1 and S1, B2 and S2, . . . , Bn and Sn. Therefore, the D/A converter 7 receives the corresponding subtraction currents Is1 and Is2 from the differential subtracter 3 in response to signals indicative of the result of conversion of the higher bits, i.e., the complementary digital signals S1-Sn and B1-Bn.
The differential subtracter 3 includes npn transistors Q1 and Q2, emitter resistors R.sub.E1 and R.sub.E2, collector resistors Rc1 and Rc2, and a current supply CS0. The transistor Q1 has a base electrode receiving an output voltage V1 from the sample hold circuit 2. The transistor Q2 has a base electrode receiving an output voltage V2.
FIG. 9 is a signal waveform diagram showing an operation of the differential subtracter 3 shown in FIG. 5. It is assumed that a differential input voltage .DELTA.Van having a triangular waveform shown in FIG. 9 is applied to the A/D converter 100 shown in FIG. 5. Thus, the sample hold circuit 2 applies the differential voltages V1 and V2 shown in FIG. 9 to the differential subtracter 3. FIG. 9 shows a current Iv1 corresponding to the voltage V1.
The D/A converter 7 shown in FIG. 5 supplies the differential current signals Is1 and Is2 corresponding to the result of conversion of the higher bits. The differential current signal Is1 is shown in FIG. 9. The current signals Iv1 and Is1 each are applied to the differential subtracter 3 shown in FIG. 5, and the subtraction is executed between the current signals Iv1 and Is1. The differential voltage signals indicative of the result of subtraction, i.e., the differential subtraction signals Vo1 and Vo2 are shown in FIG. 9.
The differential voltage signals Vo1 and Vo2 are applied to the lower bit A/D converter 8, and are subjected to the conversion by the A/D converter 8, using the fine reference voltage Vfr. The conversion by the lower bit A/D converter 8 is similar to that by the higher bit A/D converter 6, and thus description is not repeated.
Referring to FIG. 9 again, the subtraction by the differential subtracter 3 will be described below in view of a circuit operation. In the following description, "I.sub.E1 " and "I.sub.E2 " indicate emitter currents of the transistors Q1 and Q2, respectively. "Ic1" and "Ic2" indicate collector currents of the same, respectively. "V.sub.BE1 " and "V.sub.BE2 " indicate the base-emitter voltages. "V.sub.x " indicates a voltage at a common node of emitter resistors R.sub.E1 and R.sub.E2 each having a resistance R.sub.E. It is also assumed that a constant current 2.multidot.I0 flows through the constant current supply CS0 and that the resistors Rc1 and Rc2 each have a resistance Rc.
In the case where the voltage signal V1 is equal to the voltage signal V2 (V1=V2), there exists a relationship of I.sub.E1 =I.sub.E2 =Tc1=Tc2=I0. Owing to relationships of Vo1=Vcc-Rc.multidot.Ic1 and Vo2=Vcc-Rc.multidot.Ic2, the output voltages Vo1 and Vo2 have the same voltage level.
In the case where the voltage V1 is larger than the voltage V2 (V1&gt;V2), there exist following relationships. EQU I.sub.E1 =(V1=V.sub.BE1 -V.sub.x)/R.sub.E =IC1 (1) EQU I.sub.E2 =(V2-V.sub.BE2 -V.sub.x)/R.sub.E =IC2 (2) EQU Vo1=Vcc-Rc.multidot.Ic1 (3) EQU Vo2=Vcc-Rc.multidot.Ic2 (4)
In this case, since the collector current Ic1 is larger than the collector current Ic2 (Ic1&gt;Ic2), the output voltages Vo1 and Vo2 have a relationship of Vo1&lt;Vo2.
In addition to the basic differential operation described above, the differential subtracter 3 carries out the subtraction for the subtraction currents Is1 and Is2. In the case of V1&gt;V2, the subtraction currents Is1 and Is2 having the relationship of Is1&lt;Is2 are drawn from the differential subtracter 3 into the D/A converter 7. This changes ranges of the output voltages Vo1 and Vo2 of the differential subtracter 3 into ranges which allow processing by the lower bit A/D converter 8.
Meanwhile, in the case of V1&lt;V2, a similar operation is carried out in a manner opposite to the foregoing. In this case, the subtraction currents having the relationship of Is1&gt;Is2 are drawn from the differential subtracter 3 into the D/A converter 7, and the ranges of the output voltages Vo1 and Vo2 are likewise changed into ranges for the lower bit A/D converter 8.
As described above, the subtraction using the subtraction currents Is1 and Is2 reduces the difference (=.vertline.Ic1-IC2.vertline.) between the collector currents Ic1 and Ic2 into a very small value. Meanwhile, the emitter currents I.sub.E1 and I.sub.E2 are increased and reduced in response to the corresponding applied base currents V1 and V2, respectively. Therefore, a large difference may be generated between the emitter currents I.sub.E1 and I.sub.E2 in some cases. More specifically, when the applied differential voltage defined by the voltage signals V1 and V2 is large, one of the emitter currents I.sub.E1 and I.sub.E2 becomes large and the other becomes small. Imbalance between the emitter currents I.sub.E1 and I.sub.E2 may cause the following disadvantage.
In general, the base/emitter voltage V.sub.BE can be expressed by the following expressions. EQU V.sub.BE -V.sub.T .multidot.ln (.alpha..multidot.I.sub.E /Isat)(5) EQU I.sub.E1 =I0+I.sub.R ( 6) EQU I.sub.E2 =I0-I.sub.R ( 7) EQU I.sub.R ={(V1-V.sub.BE1)-(V2-V.sub.BE2)}/R.sub.E ( 8)
where V.sub.T is a thermal voltage, .alpha. is a current amplification rate, and Isat is a saturation current.
From the expression (5), it can be understood that the base-emitter voltage V.sub.BE of the transistor is a function of the emitter current I.sub.E. Therefore, the difference between the base-emitter voltages V.sub.BE1 and V.sub.BE2 cannot be ignored if the emitter current I.sub.E1 is much larger than the emitter current I.sub.E2 in the differential subtracter 3 shown in FIG. 8.
More specifically, as can be seen from the foregoing expressions (1) and (2), since the collector currents Ic1 and Ic2 are functions of the voltages V.sub.BE1 and V.sub.BE2, the difference between the voltages V.sub.BE1 and V.sub.BE2 affects the collector currents Ic1 and IC2. The collector currents Ic1 and Ic2 are varied by the input voltages V1 and V2 as well as the voltages V.sub.BE1 and V.sub.BE2, so that the differential subtracter 3 cannot execute the accurate subtraction. In other words, the accuracy in the subtraction deteriorates. This reduces the accuracy in the A/D conversion of the lower bits.
Additionally, there is a second disadvantage described below. For simplicity, it is assumed that both the subtraction currents Is1 and Is2 shown in FIG. 8 are 0 in the following description. FIG. 10 is a waveform diagram showing the changes of the differential input voltage .DELTA.Van and differential output voltages Vo1 and Vo2 in this case. For example, at time t1, the differential input voltage .DELTA.Van (=V1-V2) is maximum. At this time, the output voltage Vo2 nearly attains the supply voltage level Vcc, and the output voltage Vo1 equals to Vcc-2.multidot.Rc.multidot.I0.
FIG. 11 is an enlarged waveform diagram showing the output voltages Vo1 and Vo2 shown in FIG. 10. For example, the output voltage Vo2 has an amplitude of 2.multidot.Rc.multidot.I0, as shown in FIG. 11. As described above, the A/D conversion for the lower bits is carried out after the subtraction with the subtraction currents indicative of the result of A/D conversion of the higher bits. In FIG. 11, therefore, there is a delay .DELTA.t' from the sampling of the input voltage at time t11 to the output of the output voltage Vo2 indicative of the result of subtraction at time t13. The existence of the delay time .DELTA.t' prevents the accurate subtraction in the differential subtracter 3. In particular, this disadvantage becomes significant in the A/D converter requiring a high operation speed.